Deskewing of timing signals involves compensating for various parameters that may introduce delays between two or more timing signals which may result in the timing signals being unsynchronized. Deskewing may be necessary at either the output of a device or internally to the device. One parameter that may introduce delays is the power supply operating voltage. Deskewing may also be necessary for two signals generated from a single signal or for two signals that are deskewed at one power supply voltage value after which one signal is translated to a new power supply voltage value. Modern Central Processing Units (CPUs) and microprocessors generally tend to reduce the power supply operating voltages in order to reduce power consumption and increase the chip density, as well as for other performance considerations. Due to other design considerations, memory devices, such as dynamic random access memories (DRAMs) may operate at different supply voltages than the CPU. In a configuration where the CPU operates at a first supply voltage and the DRAM operates at a second supply voltage, the timing clocks associated with each device must generally be properly deskewed to maintain proper synchronization between the devices. One such configuration occurs with modern microprocessors which may operate at a 2.5 volt supply voltage, while DRAM chips generally operate at a 3.3 volt supply voltage.
Referring to FIG. 1, a previous approach deskewing circuit 10 is shown. The circuit 10 generally comprises an input 12, an output 14, an output 16 and a zero delay buffer 18. The input signal 12 generally receives a 2.5 volt supply clock that is presented directly to the output 14. The clock received at the input 12 is also presented to the zero delay buffer 18 which is then presented at the output 16. The zero delay buffer generally provides a conversion from a 2.5 volt supply clock to the 3.3 volt supply clock presented at the output 16. The zero delay buffer 18 may be based on a phase locked loop (PLL) implementation or even a delay-locked look (DLL).
The deskewing circuit 10 generally requires a large amount of silicon area to implement the a PLL or DLL. The amount of time delay between the two logic paths running at separate supply voltages is in the order of 2.about.5 ns. A relatively complex zero delay buffer 18 may be required to accurately deskew the 2.about.5 ns delay which, while possibly being practical on a board level design, is generally too large and complex a solution to be implemented directly on an integrated circuit. As a result, an approach that requires less area to implement is generally desired.
Referring to FIG. 2, a second previous approach deskewing circuit 30 is shown. The circuit 30 generally comprises an input 32, a programmable delay block 34, a logic block 36, an output 38 and an output 40. The input 32 generally receives a 3.3 volt supply clock which is generally presented to both the delay block 34 and to the logic block 36. The programmable delay block 34 generally has an input 35 which receives a trim control signal that generally programs the amount of delay introduced by the programmable delay block 34. The output 38 presents a 3.3 volt supply clock. The logic block 36 generally receives the 3.3 volt supply clock and provides a conversion to a 2.5 volt supply clock which is generally presented at the output 40. The programmable delay block 34 is generally used to provide the deskewing function of the circuit 30. The logic block 36 generally operates from a separate supply voltage to convert the output 40 to the 2.5 volt supply clock. The conversion of supply voltages creates a certain amount of delay, which is generally compensated for by the delay block 34.
The circuit 30 relies on the fact that a lower supply voltage generally causes a path to be slower. A disadvantage with the circuit 30 is that it relies on an open loop architecture. A single input 35 is used to determine the amount of delay presented by the delay block 34. As a result, as both power supplies vary, the delay between the output 38 and the output 40 will also vary. The output 38 and the output 40 may also vary in response to variations in processing. Under certain tolerant specifications, the circuit 30 may provide an adequate solution. However, in more stringent specifications, the power supply specification may vary from 2.5 volts to 3.3 volts and beyond while requiring a deskewed relationship, which the circuit 30 cannot provide.
Referring to FIG. 3, a third previous approach deskewing circuit 50 is shown. The circuit 50 generally comprises an input 52, a delay block 54, a variable delay block 56, a delay detector 58, an output 60 and an output 62. An input clock is generally received at the input 52 which operates a 3.3 volt supply voltage. The input clock received at the input 52 is generally presented to both the delay block 54 and the variable delay block 56. The delay block 54 generally presents a fixed amount of delay prior to presenting a 3.3 volt supply clock at the output 60. The delay block 56 presents a variable delay prior to presenting a 2.5 volt supply clock at the output 62. The delay detector 58 generally receives a feedback of both the 2.5 volt supply voltage clock from the output 62 and the 3.3 volt supply voltage clock from the output 60 and calculates a phase difference which is presented to an input 57 of the variable delay block 56. In response to the feedback signals, the variable delay block 56 adjusts for the actual delay between the output 60 and the output 62. The circuit 50 generally allows for deskewing of the outputs 60 and 62 at the output pad level. A problem associated with the circuit is that the output pads associated with a 2.5 volt and 3.3 volt signal have different propagation delays. As a result, the path through the output pads must be included in the deskewing loop as shown in FIG. 3.
While the circuit 50 has the advantage that it adjusts for process and power supply variations, it suffers from drawbacks associated with the presence of power supply noise. During situations where there is a sufficient amount of power supply noise, it is possible for the deskewing relationship between the outputs 60 and 62 to be lost.